The invention relates to an electronic driver circuit for word lines in a memory matrix and also to a memory apparatus, in particular a magneto-resistive random access memory (MRAM) apparatus.
Semiconductor memories normally contain a cell array having a matrix of column and row lines, otherwise known as word and bit lines, at whose points of intersection the respective memory cell is located. In this case, the word line in a memory component is used for addressing during read and write operations, and the bit line is used for reading or writing to the memory cell.
The memory elements used in an MRAM memory cell are typically magnetic tunnel elements (TMR elements; TMR: tunnelling magnetoresistance). Such a TMR element contains, in principle, two magnetic layers, a hard magnetic layer and a soft magnetic layer. The layers are isolated from one another by an insulating intermediate layer having a thickness of only a few atomic layers. The magnetizations in the two layers may have both the same direction and opposite directions. The insulating barrier between the magnetic layers is so thin that, after a voltage has been applied, a few electrons can pass; a xe2x80x9ctunnel currentxe2x80x9d flows. In this context, the level of the tunnel current depends on the orientation of the magnetization directions with respect to one another.
Such a memory is written to by applying an electric current to a word line and a bit line in order to stipulate the magnetization direction of the xe2x80x9csoftxe2x80x9d magnetic layer. The direction of the currents determines the content of the memory element. The currents required are relatively high (approximately 2.5 mA), particularly for writing, since the magnetization is produced by overlaying the magnetic fields of the currents in the word line and bit line.
For a read operation, a defined voltage is applied to the word line of the selected memory cell, and the defined voltage should be different from the voltage of the selected bit lines. On the bit lines running perpendicular to the word lines, it is then possiblexe2x80x94depending on the nature of the evaluation circuit on the bit linesxe2x80x94to evaluate a reading current or a reading voltage, which vary depending on the content of the addressed memory cell.
A requirement of the driving conditions is that each word line in a memory matrix in an MRAM component needs to be driven by in some cases very powerful transistors, which take up a relatively large area in integrated circuits. The transistors should be able to switch the high writing currents and to provide various voltage potentials for the un-activated and activated word lines. For the word lines in an MRAM cell array which are situated extremely close together, a special configuration is therefore required in order to minimize the area requirement and wiring complexity of the word line driver circuit.
It is accordingly an object of the invention to provide an electronic driver circuit for word lines in a memory matrix and a memory apparatus which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which allows the wiring complexity and the area of the driver circuit to be reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic driver circuit for word lines in a memory matrix. The driver circuit contains a driver source having a plurality of outputs and the outputs include coded outputs, and a plurality of word line switches connected between the outputs of the driver source and the word lines such that the outputs of the driver source are switchably connected to the word lines. The word line switches receive and are driven by a control signal.
The invention provides that such a driver circuit for word lines in the memory matrix has the driver source, preferably the current/voltage source, having a plurality of outputs and a plurality of word line switches. The word line switches switchably connect the outputs of the driver source to the word lines. The outputs of the driver source have a plurality of coded outputs, which are connected to the word lines by the word line switches, the word line switches being selected by one or more control signals. The coded outputs supply the necessary signals for reading and writing to memory cells on a word line.
The inventive concept is that a number of word lines are first selected and the coded outputs of a driver source are applied thereto. In this context, the coded outputs of the driver source are isolated from the unselected word lines by the appropriate word line switches. The driver circuit makes it possible to avoid providing for each of the word lines a dedicated line driver or a complex word line switch which switches through the respectively provided signals to the word line in the manner of a multiplexer. This allows the word line switches to be configured using little circuit and wiring complexity.
In one preferred embodiment, each of the coded outputs of the driver source can assume various output values, which respectively correspond to a particular operating mode of the word lines. The outputs are coded such that they provide the various output values according to the desired operating mode of the respective word line. The respective output, which is in each case switched through to only one of the word lines, is coded on the basis of addressing provided for the respective word line and for the operating mode provided at that point. The fact that the word line signals are actually coded in the driver source results in that the circuit complexity for the word line switches can be significantly reduced. The various output values can be current values or voltage values.
Preferably, another provision is that the outputs of the driver source contain at least one further output, which is switched through to all the word lines, which are not selected by the control signal. This ensures that the inactive word lines are at a fixed potential and do not assume an undesirable voltage by floating.
Another provision in accordance with one preferred embodiment may be that the circuit receives a plurality of control signals, each of which controls a number of the plurality of word line switches, and that at most one of the control signals switches through the coded outputs of the driver source to the respective word lines via the word line switches. In this way, in each case only one of the coded outputs is connected to a respective one of the word lines. This advantageously allows the number of outputs provided for the driver source to be reduced. The word lines are thus subdivided into a plurality of blocks, each of the blocks having a number of word lines, which corresponds to the number of coded outputs of the driver source. In this context, it is expedient to weigh the respective circuit and wiring complexity arising when a driver source having a number of outputs is produced and the saving on circuit and wiring complexity for the word line switches against one another.
Preferably the word line switches are in the form of transistors. This has the advantage that the switches are easy to produce in integrated circuits. In integrated circuits, it is also expedient, for technological reasons, to provide metal oxide semiconductor (MOS) transistors as switching elements. These additionally have low losses, i.e. the control input has virtually no current, which results in that little driver power is required when driving a plurality of such control inputs, e.g. using the control signal.
Preferably, the coded outputs of the driver source are switchably connected to the word lines by first transistors, and the further outputs of the driver source are connected to the word lines using second transistors. In this context, the first transistors are preferably chosen so that they turn on when selected by the control signal, and the second transistors are chosen so that they turn off in the case of the same control signal. The coded outputs are then connected to the word lines as a result of being selected by the control signal. The further outputs are consequently applied to the word lines not selected by the control signal by the second transistors. This advantageously ensures that, according to selection, either the coded outputs or the further outputs are connected to the word lines, which defines the respective operating mode of a word line.
Preferably, provision may be made for the first transistors to be N-MOS transistors, and for the second transistors to be P-MOS transistors and to be connected to a respective word line, the first and second transistors being controlled by the control signal. This is advantageous because N-MOS transistors and P-MOS transistors can be operated in complementary fashion, so that they can be addressed using only one control signal.
In accordance with one preferred embodiment, provision is also made for the first and second transistors to be N-MOS transistors which are controlled by two control signals such that in each case only the first transistor or only the second transistor on each of the word lines is on, and the other one is off. This is advantageous because N-MOS transistors have a smaller area than P-MOS transistors for the same power and are able to switch voltage levels in other ranges.
Preferably, a first voltage potential is present at at least one of the coded outputs, and a second voltage potential is present at the further output of the driver source, the first and second voltage potentials being approximately the same. When changing between a write and a read operation, the voltage potential of all unselected word lines and all inactive word lines, i.e. word lines which are not in a read or write mode, should preferably remain unchanged, since a flow of current through the unaddressed memory elements also needs to be prevented as far as possible in this case.
In one preferred embodiment, four word lines activated by one control signal are provided, since this allows the area of the circuit complexity to be minimized for the word lines.
Generally, the number of word lines selected by a control signal can be assumed to be arbitrary, however.
Preferably, that output of the driver source, which is connected to an active word line by an appropriate word line switch outputs a current for the purpose of writing to the memory matrix. Such a writing current on the word line permits writing to, by way of example, TMR memory elements in MRAMs.
In one preferred embodiment, that output of the driver source, which is connected to an active word line by the appropriate word line switch, outputs a reading voltage for the purpose of reading from the memory matrix. The reading voltage should be different than the voltage on the unselected word lines. This is necessary to ensure that a current flows through the TMR memory cell only via the active word line. If the voltages were the same, this would possibly result in a flow of current through a plurality of TMR elements, which would mean that it would no longer be possible to establish that memory cell through which the current were flowing, and it would thus no longer be possible to read the content of the individual memory cell.
In addition, a memory apparatus having an inventive driver circuit is preferably provided. The circuit complexity for the word line drivers can be greatly reduced in this apparatus, which allows the word line spacing to be reduced.
In this regard, another provision is made in the memory apparatus in that the two ends of the word lines can be respectively provided with the inventive driver circuit. This allows parasitic flows of current to be reduced. In this context, however, it is necessary to ensure that, when impressing currents on to the respective active word line, the output currents of the coded driver source have the same magnitude, but different arithmetic signs at the two ends.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electronic driver circuit for word lines in a memory matrix and a memory apparatus, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.